基于锁定时间分析的锁相环频率合成器

Phase-Locked Loop Frequency Synthesizer Based on Lock Time Analysis

摘要: 提出了一种新的针对采用二阶无源滤波器的锁相环频率合成器锁定时间的估算公式，并通过仿真软件及实测结果对该公式进行了验证。基于该估算公式，设计了一种具有快速锁定功能的锁相环频率合成器。实验结果表明该锁相环频率合成器锁定时间小于7μs，具有快速锁定的功能。同时该锁相环还具有良好的相位噪声性能，对于32GHz输出信号相位噪声为-72dBc/Hz@1kHz以及-90dBc/Hz@1MHz。

Abstract: In this paper, a new estimation formula for lock time of phase-locked loop (PLL) frequency synthesizer utilizing second order passive filter is proposed. The formula is verified by simulated and measured results. Then a fast-locking PLL frequency synthesizer is designed based on the estimation formula. Experimental results show that the lock time is less than 7μs which means the PLL has a good performance of fast-locking. Experimental results also show that the PLL has a good phase noise performance of -72dBc/Hz@1kHz and -90dBc/Hz@1MHz at 32 GHz.