Abstract: The paper presents the work on a 14 GHz 8 bit ROM-Less direct digital synthesizer (DDS) in 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology having ft 250/ fmax 280 GHz. The sine-weighted nonlinear digital to analog converter (DAC) is adopted to achieve a phase-to-amplitude ROM-Less architecture, which can make the best of speed advantage of the InP DHBT technology for medium to large scale mixed signal integrated circuit. A simplified pipelined phase accumulator is used to reduce power consumption. Over the full range of frequency control words (FCWs), the average spurious free dynamic range (SFDR) is 24.8 dBc. The circuit is implemented with 2122 transistors consuming 2.4 W of power and has a figure of merit (FOM) of 5.83 GHz/ W.