Signal Integrity Simulation Method of DDR4 SDRAM System Based on ANSYS

With the development of semi-conductor technology, the signal integrity of DDR SDRAM is becoming a big challenge for designers. This paper proposes a signal integrity simulation method of DDR4 SDRAM based on ANSYS and IBIS 5. 0 Model. The signal integrity of high speed circuit board with DDR4 SDRAM is simulated more accurately by using the data of composite current and synchronous switching output current added in IBIS 5. 0 Model. The simulation results demonstrate that the amplitude and eye diagram of high speed signals are deteriorated obviously after signals go through PCB wires and packages. After adding decoupling capacitor to the power supply of the simulation circuit, jitter and SSN of the transmitter and receiver are significantly improved. When the input signal is changed from PRBS code to DBI signal without decoupling capacitor, SSN of the receiver is improved, and the power consumption of the device can be reduced to half of the original.